Embodiments of the inventive concept described herein relate to a semiconductor memory device, and more particularly, to an output circuit for high-speed data transfer.
A semiconductor memory device may have an output driver to an internal signal to an external device. A general output driver may have a PMOS transistor and an NMOS transistor that are connected in series between a power line and a ground line.
In general, a synchronous dynamic random access memory (SDRAM) may operate in a single data rate (SDR) technique, in which one unit of data is input and output during one period of a clock in synchronization with a rising edge of a system clock. However, an increase in data input/output speed may be required according to an increase in frequency of the system clock. For this, there may be proposed a double data rate (DDR) technique according to which data is input and output in synchronization with rising and falling edges of the system clock, respectively. The DDR technique may enable data to be transferred at high speeds without increasing internal operation frequency. Also, in recent years, a low power DDR (LPDDR) technique has been proposed that enables data to be transferred at higher speed using less power. However, with the conventional LPDDR techniques, the period for high-speed data transfer of multiple data signals to output pads may be relatively long. Therefore, when the system clock frequency increases, inter-symbol interference of the data likewise increases.